Für die Produktivitätssteigerung beim Systementwurf in der Mikroelektronik ist der konsequente Einsatz wiederverwendbarer Komponenten (IP: Intellectual Property) unverzichtbar. Das Vorhaben IPQ setzt mit dem Schwerpunkt "IP-Qualifikation" dort an, wo noch erhebliche Probleme bei der Realisierung einer IP-basierten Entwurfsmethodik bestehen. Die im Vorhaben IPQ zu entwickelnden Methoden und Tools sollen es ermöglichen, entscheidende Verbesserungen für die Qualitätssicherung bei der Anwendung und Entwicklung von IP-Modulen zu erzielen. Dies beinhaltet Spezifikationsmethoden, intelligente IP Suche, Eingangscheck, Verfahren zur IP Anpassung und Beiträge zur Standardisierung.
Mehr Informationen über IPQ hier
TOOLIP's (Tools and Methods for IP) main goal is to address the complexity of current system design in networking, high-speed links, multimedia and automotive domains by using system-level modeling and verification techniques, applying design reuse with qualified and parametric IP cores, and providing a seamless design flow integrating existing and emerging tools. The industrial partners and their applications will be the driving forces of TOOLIP. The close cooperation of IP users, IP providers, designers and research institutes constitutes one of the major potentials of the consortium. TOOLIP will be crucial to the positioning of European industry, since the IP-based system-level modeling and simulation design methodology represents a breakthrough in current design methodology, which would lead to a strong impact on competitiveness and standardization. Furthermore, TOOLIP will enable the improvement of developed tools and possible future commercialization. By establishing a team with the required know-how, TOOLIP will also present new business opportunities, which would facilitate the creation of spin-off companies.
Find out more about ToolIP here.
The MILOS Project (Minimally Invasive Long-term Organisational Support) is a joint project of the Artificial Intelligence Group at the University of Kaiserslautern and the Software Process Support Group at the University of Calgary.
Software engineering processes are highly creative and therefore prone to frequent changes through both, the planning phase and process enactment. Software projects often extend over a long period of time making it impossible to plan the project in detail before process execution starts. Information necessary to complete the plan may not be available at the planning stage but is gathered as part of the process itself. Due to the long project duration, and to the fact that experience with a particular kind of software project is often gained only while executing this project, project plans often turn out to be inadequate. Further, products of the software process are seldom correct "at first try". Usually, several rework circles have to be done, with changes made to products, which in turn necessitate more changes to keep products consistent with each other. In large, distributed software projects, these changes can easily lead to problems: some concerned people may not be informed of the change in time to adjust their own products before a deadline, or perhaps are not notified of the change at all.
Find out more about MILOS here.
The VEGA (Validation and Exploration by Global Analysis) research project aims to provide a structured framework for the VALIDATION and EXPLORATION of knowledge bases (KBs) by global analysis. This knowledge EVOLUTION framework will be offered to developers and users of KBs. While much knowledge is acquired and represented in KBs, often its interconnections remain unexplored (lack of discovery support) and its content is not validated (lack of quality control). Expert systems accessing such KBs suffer from the resulting brittleness. Knowledge engineers shall thus interact with the VEGA system for evolving (i.e., exploring and validating) KBs represented in a highly portable (declarative) language.
Find out more about VEGA here.
Prof. Dr. Klaus-Dieter Althoff
Institut für Informatik
Bereich Intelligente Informationssysteme
Institut für Informatik
Sekretariat: Raum A8b Spl,
Telefon +49 5121 883 -750